The present invention relates to a solid-state imaging device, such as a complementary metal-oxide semiconductor (CMOS) image sensor, having a photoelectric converter and a plurality of pixel transistors for every pixel in a two-10 dimensional array.
FIG. 8 is a circuit diagram showing an example of the pixel structure used in a known CMOS image sensor.
Referring to FIG. 8, each pixel includes a photoelectric converter 1 and a plurality of transistors 2, 3, 4, and 6.
The photoelectric converter 1, such as a photodiode, receives light and stores signal charge.
The transistor 2 amplifies the signal charge (hereinafter referred to as the amplifying transistor 2). The transistor 3 transfers the signal charge stored in the photoelectric converter 1 to the gate electrode of the amplifying transistor 2 (hereinafter referred to as the transfer transistor 3).
The transistor 4 resets the voltage of the gate electrode of the amplifying transistor 2 (hereinafter referred to as the reset transistor 4).
A signal line 5 is used for supplying a power-supply voltage (hereinafter referred to as the power-supply voltage supply line 5). The drains of the reset transistor 4 and the amplifying transistor 2 are connected to the power-supply voltage supply line 5.
The transistor 6 selects an output pixel (hereinafter referred to as the selection transistor 6). A signal line 7 is used for outputting a pixel signal (hereinafter referred to as the pixel output line 7).
An external transistor 8 supplies a constant current to the pixel output line (hereinafter referred to as the constant-current supply transistor 8). The constant-current supply transistor 8 supplies a constant current to the amplifying transistor 2 in a selected pixel to cause the amplifying transistor 2 to serve as a source follower, so that a voltage differing from the voltage of the gate electrode of the amplifying transistor 2 by a predetermined value is applied to the pixel output line 7.
A signal line 9 is a transfer signal line used for controlling the voltage of the gate electrode of the transfer transistor 3 (hereinafter referred to as the transfer signal line 9). A signal line 10 is a reset signal line used for controlling the voltage of the gate electrode of the reset transistor 4 (hereinafter referred to as the reset signal line 10). A signal line 11 is a selection signal line used for controlling the voltage of the gate electrode of the selection transistor 6 (hereinafter referred to as the selection signal line 11). A signal line 12 is a constant-voltage supply line used for supplying a predetermined voltage to the gate electrode of the constant-current supply transistor 8 such that the constant-current supply transistor 8 performs a saturation region operation to supply a predetermined current (hereinafter referred to as the constant-voltage supply line 12).
A terminal 13 is a pulse terminal through which a transfer pulse is supplied to each transfer signal line 9, and is connected to one input port of each line-selection AND element 14. An output from vertical selection means 15 is supplied to the other input port of the line-selection AND element 14. The output port of the line-selection AND element 14 is connected to the transfer signal line 9.
A terminal 16 is a pulse terminal through which a reset pulse is supplied to each reset signal line 10, and is connected to one input port of each line-selection AND element 17. The output from the vertical selection means 15 is supplied to the other input port of the line-selection AND element 17. The output port of the line-selection AND element 17 is connected to the reset signal line 10.
A terminal 18 is a pulse terminal through which a selection pulse is supplied to each selection signal line 11, and is connected to one input port of each line-selection AND element 19. The output from the vertical selection means 15 is supplied to the other input port of the line-selection AND element 19. The output port of the line-selection AND element 19 is connected to the selection signal line 11.
In the structure described above, the control pulses are supplied only to the signal lines of a pixel line selected by the vertical selection means 15.
A readout operation from each pixel is performed in a manner described below with drive signals shown in FIG. 9 being supplied.
Referring to FIG. 9, a selection signal is supplied to the selection signal line 11 in FIG. 8, a reset signal is supplied to the reset signal line 10 in FIG. 8, and a transfer signal is supplied to the transfer signal line 9 in FIG. 8.
First, the selection transistor 6 and the reset transistor 4 in the pixel line for which the readout operation is to be performed are brought into conduction to reset the gate electrode of the amplifying transistor 2. After the reset transistor 4 is brought out of conduction, a voltage corresponding to the reset level of each pixel is supplied to a downstream correlated double sampling (CDS) circuit 20.
Next, the transfer transistor 3 is brought into conduction and the electric charge stored in the photoelectric converter 1 is transferred to the gate electrode of the amplifying transistor 2. After the transfer is completed and the transfer transistor 3 is brought out of conduction, a voltage having the signal level corresponding to the amount of stored charge is supplied to the downstream CDS circuit 20.
The CDS circuit 20 measures the difference between the reset level that has been read out and the signal level and suppresses a fixed pattern noise produced due to, for example, the variation in the threshold (Vth) of the transistor read out for every pixel.
The signal stored in the CDS circuit 20 is selected by column selection means 21 and is read out in a downstream circuit, such as an automatic gain control (AGC), through a horizontal signal line 22 for processing.
As described above, each pixel in the CMOS image sensor must include the various transistors and the control signal lines for reading out the electric charge stored in the photoelectric converter, in addition to the photoelectric converter.
Accordingly, it is difficult to reduce the pixel size in the CMOS image sensor, compared with a charge coupled device (CCD) image sensor having a simple pixel structure.
Consequently, a solid-state imaging device that eliminates the use of a selection transistor, as shown in FIG. 11, by changing the drive method of the pixel circuit to simplify the pixel structure is proposed (for example, Japanese Unexamined Patent Application Publication No. 2002-077731).
Alternatively, for example, as shown in FIG. 12, a metal oxide semiconductor (MOS) image pickup device in which one amplifying transistor is shared between a plurality of photoelectric converters for readout is proposed (for example, W097/07630).
Specifically, in pixels shown in FIG. 12, the outputs from the two photoelectric converters in the two adjoining pixels are supplied to the gate electrode of one amplifying transistor 2 through the transfer transistors 3. Sequentially controlling the transfer transistor 3 and the 20 reset transistor 4 outputs two pixel signals from the amplifying transistor 2.
The MOS image pickup device is structured such that a capacitor 23 is connected to the gate electrode of the amplifying transistor 2 and a kick pulse is supplied through a capacitor kick line 24 to control the voltage at the gate electrode.
In the related art shown in FIG. 12, sharing the amplifying transistor can decrease the number of elements in one pixel to reduce the pixel size. However, all the pixels in the pixel array have the same shape in the unit cell (including one pixel) shown in FIGS. 8 and 11, whereas the pixel array having the unit cells (pairs of pixels sharing the amplifying transistor), shown in FIG. 12, includes the two kind of pixels.
Since the two kinds of pixels have different arrangements of elements, there are differences in characteristics, such as the sensitivity and the saturation, between the two kinds of pixels.
For example, when color coding is performed in a Bayer format, the pixels coded in G have different characteristics for every line. As a result, there is a problem in that horizontal stripes are drawn in one image.
This problem involves not only the unit cells in FIG. 12 but also the sharing of the transistors between the pixels, regardless of the number or arrangement of the transistors.
Since the capacitor 23 is provided only in the lower pixel in FIG. 12, for example, incident light is shaded due to the capacitor 23 or the light receiving area is reduced in size due to the occupancy of the capacitor 23 to decrease the quantity of incident light. Accordingly, the sensitivity in the lower pixel becomes lower than that in the upper pixel.
Furthermore, the two kinds of pixels differ from each other in the arrangement of the transfer transistor for reading out the electric charge subjected to the photoelectric conversion and, also, in the direction of reading out the electric charge. The difference in arrangement of the transfer transistor, the arrangement determining the direction of reading out the electric charge, causes a difference in sensitivity between the two kinds of pixels. This is because, for example, the effect of the potential of the transfer transistor on the potential of the light receiving section occurs in different positions in the two kinds of pixels and, therefore, the two kinds of pixels possibly differ from each other in the photoelectric conversion efficiency of light being incident from the same direction or the amount of stored charge.
In a known readout method, for example, a signal output read out from each pixel to the CDS circuit is processed in one output system (the horizontal signal line, the AGC, an analog-to-digital converter (ADC), etc.) to be converted into a digital signal and, then, the digital signal is processed in inner and external circuits and extracted.
However, in recent years, in response to the need for a solid-state imaging device capable of performing sampling at a higher speed, a method of dividing signal outputs, read out from each pixel to the CDS circuit, into two output systems for processing, as shown in FIG. 13, is proposed.
FIG. 13 shows an example of the overall structure of a CMOS image sensor. Referring to FIG. 13, the CMOS image sensor includes a sensor 111 including the pixel array described above, a vertical drive circuit 112, a shutter drive circuit 113, a CDS circuit 114, a horizontal drive circuit 115, a timing generator 116, AGC circuits 117A and 117B, ADC circuits 118A and 118B, and so on. The CMOS image sensor is structured such that signals are output through two horizontal signal lines 119A and 119B, the AGC circuits 117A and 117B, and the ADC circuits 118A and 118B.
The division of the output system into two halves the load on one horizontal signal line, so that it is possible to perform the readout at double speed, compared with a known image sensor having one output system.
However, it is not possible to make the characteristics of the elements in the two output systems equal in terms of processing. In other words, since the output systems include analog circuits, such as the AGC and the ADC, which differ in gain, noise characteristics, or the like, signals that are slightly different from each other are output after signal processing even when the same signals are input.
Particularly, in the solid-state imaging device in question, analog signals having low levels of the order of a few millivolts to ten to the minus first power millivolts are processed as the signals output from the pixels and, thus, the difference in the characteristics between the output systems causes a large problem.
For example, FIG. 14 illustrates a manner in which signals are read out from an imager using a Bayer color filter through two output systems.
In the Bayer array shown in FIG. 14, RG lines having R pixels and Gr pixels alternatively arranged are arranged adjacent to GB lines having Gb pixels and B pixels alternately arranged.
In the readout from the RG line (the n-th line) in FIG. 14, the signals are read out from the R pixels through an output system A and are read out from the Gr pixels through an output system B.
In the readout from the GB line (the n+1-th line) in FIG. 14, the signals are read out from the Gb pixels through the output system A and are read out from the B pixels through the output system B.
In other words, the signals are read out from the R pixels and the Gb pixels through the output system A, and the signals are read out from the B pixels and the Gr pixels through the output system B.
Since the signals read out from the R, G, and B pixels are subjected to signal processing, such as adjustment of color balance, for every color downstream, a small difference between the R, G, and B pixels due to the output systems does not cause a large problem.
However, when there is a small difference between the Gr and Gb pixels, which are processed through the different output systems while being processed as the same G pixels, the signals periodically vary in the line direction, thus possibly resulting in horizontal stripes in one image.
Accordingly, it is an object of the present invention to provide a solid-state imaging device capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided.